Mobile Multimedia Systems Group

We are designing highly energy-efficient machine learning processors by developing both hardware-friendly algorithms and low-power hardware design techniques. Our ultimate goal is to build practical machine-learning processors that exhibit both state-of-the-art algorithm performance and energy efficiency by finding the best algorithm-hardware combination. For instance, we developed a neuromorphic processor implementing an SNN (Spiking Neural Network), which achieved substantially better energy efficiency while closely matching conventional deep learning in accuracy. Conventional deep learning algorithms indeed demonstrate excellent performance across many tasks, but often they are not suitable for hardware implementation due to excessive amount of computation and memory requirements. We aim to optimize state-of-the-art deep learning algorithms to make them suitable for hardware implementation by significantly lowering computational overheads. We recently demonstrated a reliable low-precision training algorithm with minimal accuracy degradation, allowing for the use of lightweight arithmetic units and lowering memory access overheads. Digital CMOS circuits offer very reliable operation and are easy to design with, but they have certain limits on the achievable performance and efficiency. We are trying to overcome this limitation by adopting various circuit techniques in machine learning systems. One example is in-memory computing circuits, which improve energy efficiency through analog or mixed-signal operation on various deep learning models. Power supply regulation is one of the key challenges in modern large-scale digital SoCs. We look into both on-chip and off-chip approaches to reliably regulate power supply while mitigating common design issues. In addition, we aim