차세대 반도체 소자 연구실

성균관대학교 반도체 소자 연구실 (SungKyunKwan University Device Research Laboratory, SKKU-DRL)에서는 전종욱 교수님과 함께 차세대 반도체 소자 최적화 및 집적회로 설계 자동화 기술 연구를 수행하고 있습니다. 특별히, 산업체에서 향후 도입 예정인 메모리(DRAM, NAND Flash, 뉴로모픽) / 파운드리 Logic / 디스플레이 / 통신 RF 응용에 대해, 산업체 기술 개발 flow에 따른 시뮬레이션기반 AI자동화 및 Digital Twin 연구를 수행중에 있습니다. 연구실 목표는 산업계 수요 기반 실무적 기술에 관한 연구 수행을 통해 차세대 반도체 기술 개발을 주도적으로 수행할 수 있는 고급 엔지니어 양성에 있습니다. PDK is a database that specifies a technology; it contains all the information required to design an IC. “Path-finding PDK“ incorporates data about future technology (device electrical properties, mask info., design rules, types and layout of cells, etc.) where options have not been decided or standardized, path-finding PDK includes various options. The designers can then make their early design studies trying out the available options. In addition, in the latest technologies, the parasitic effects such as parasitic RC delay, IR drop, local strain effect, and self-heating etc. becomes very important and they are strongly dependent on the design layout style. So, the accurate estimation of various technology options can be performed at the circuit level. That’s why we need path-finding PDK. Device engineers and designers have started to discuss exploiting the concept of virtual fabrication in order to hedge the risk arising from difficulties in optimizing many new knobs simultaneously. Concurrent optimization of design and technology based on prediction of semiconductor hardware characteristics has now become an integral component of technology development. Traditional design and technology co-optimization (DTCO) has focused on the interplay between technology (device architecture and integration) and design (design rule and layout scheme) in terms of design for manufacturability. As silicon scaling