반도체설계자동화연구실

We develop EDA methodologies for advanced stacked IC architectures, including 3D ICs with memory-on-logic and logic-on-logic integration, backside and dual-side interconnect technologies, and 2.5D chiplet systems based on interposers. We develop DRV-aware design methodologies for advanced technology nodes, focusing on robust physical design and cross-layer optimization through design-technology co-optimization (DTCO) and system-design-technology co-optimization (SDTCO). Our AI-EDA research develops intelligent algorithms for next-generation electronic design automation, spanning deep-learning-based design quality prediction, reinforcement-learning-driven design optimization, GPU-accelerated differentiable optimization, and generative AI for automated circuit and system design. We develop EDA/CAD methodologies for emerging AI chip architectures, focusing on physical design optimization for in-memory computing systems, including logic-in-memory (LiM), processing-in-memory (PIM), and compute-in-memory (CiM).