Device-to-System Integration Laboratory

As silicon field-effect transistors approach their fundamental downscaling limits, maintaining performance gains through conventional scaling has become increasingly challenging. To address these limitations, advanced device architectures—such as gate-all-around (GAA) FETs, complementary FETs (CFETs), and FlipFETs—along with emerging low-dimensional channel materials, are being actively explored for next-generation logic. Low-dimensional materials, including two-dimensional transition metal dichalcogenides (TMDs) and one-dimensional carbon nanotubes (CNTs), are particularly attractive due to their excellent electrical properties at scaled dimensions and their compatibility with low-temperature, BEOL-compatible processes. These characteristics make them promising candidates for monolithic 3D integration. enabling sequential device stacking and vertical integration. This work aims to establish a comprehensive framework for employing two-dimensional (2D) semiconductors as channel materials in transistor devices. We first investigate 2D single-flake transistors, focusing on how flake thickness and material uniformity influence electrical characteristics through systematic and statistical analyses. Building on the insights obtained from single-flake devices, we further extend our study to device fabrication using transferred 2D film-based transistor performance. Through this continuous research flow, we seek to bridge fundamental material understanding and practical device implementation of 2D semiconductor channels. This research aims to enhance performance and reliability to enable the commercialization of two-dimensional (2D) semiconductors as transistor channel materials. Focusing on logic-compatible, top-gated 2D FETs, we address key challenges arising from the ultrathi