인공지능 하드웨어 & 알고리즘

Welcome to AI Hardware and Algorithm Lab at Hanyang University. At our lab, we are at the forefront of innovating algorithms and hardware architectures for high-speed and energy-efficient artificial intelligence. Our lab specializes in the seamless integration of algorithm-hardware co-design and the optimization of deep learning software, setting new benchmarks in AI efficiency. At the intersection of algorithm brilliance and hardware robustness, we are redefining the boundaries of AI capabilities, committed to advancing the future of intelligent systems. We investigated the challenge of applying quantization-aware training (QAT) on decoder-based Transformer models like LLaMA and proposed a novel knowledge distillation (KD) method to overcome it. With our new KD, we could maintain LLM inference accuracy while compressing its model size roughly 16 times. In this work, we analyzed the shortcomings of SOTA post-training quantization (PTQ) techniques for quantizing both weight and activation, and we proposed intuitive ideas as well as a new INT4 data format to improve LLM's performance. We demonstrated that the combined efforts help recover accuracy for 4-bit weight and 8-bit activation quantization (W4A8), sacinv about 50% of hardware cost from the INT8 MAC unit. This paper propose SPADE, an algorithm-hardware co- design strategy to maximize vector sparsity in pillar-based 3D object detection and accelerate vector-sparse convolution com- mensurate with the improved sparsity. SPADE consists of three components: (1) a dynamic vector pruning algorithm balancing ac- curacy and computation savings from vector sparsity, (2) a sparse coordinate management hardware transforming 2D systolic array into a vector-sparse convolution accelerator, and (3) sparsity- aware dataflow optimiz