반도체 설계 기술 연구실

IR-drop is the voltage drop that occurs to reach the Vdd pin of the standard cell in the metal wires that make up the power grid. If IR-drop occurs and the voltage supplied to the standard cell is reduced, the performance of the standard cell can be reduced, resulting in timing violations such as setup violations. Conventional tool for analyzing IR-drops computes IR-drops by solving a large linear system of equations. But in the case of dynamic IR-drops, the larger the circuit, the more time-consuming it becomes. In this work, we aim to study a model that uses machine learning techniques to quickly predict IR drop. Power distribution network (PDN) is responsible for supplying the current from power pads to standard cells, while satisfying IR-drop constraint. Conventional PDN synthesis assumes regular PDN straps. Strap widths and pitches are determined in empirical fashion. However, as the wire resistance increases due to technology scaling, PDN requires more power straps. This causes high routing congestion. We aim to study a new PDN synthesis considering routing using machine learning. Three-dimensional integrated circuit (3D IC) is a vertical stack of multiple IC layers (as the figure shows). 3D ICs provide higher device density, higher bandwidth, and lower power consumption compared to conventional planar (2D) IC designs. However, thermal issue is a critical challenge in 3D IC. Vertically stacked multiple layers cause a significant increase in power density. Also, due to low thermal conductivity of dielectric layers, heat generated from the blocks increases the temperature inside the 3D ICs and adversely affects reliability and performance. In order to deal with this thermal issue, thermal-aware 3D IC floorplanning, considering the power consumption and overlapping p