디펜더블컴퓨팅

Increasing exponentially with technology scaling, the soft error rate in even earth-bound embedded systems manufactured in deep sub-nanometer technology is projected become a serious design consideration. ITRS and many researchers expect soft error rate to increase exponentially at every technology. A high energy radiation particle, e.g., an alpha particle, a neutron, or a free proton, may strike the diffusion region of a CMOS transistor and produce charge which can result in toggling the logic value of the gates or flip-flops. This phenomenon of change in the logic state of a transistor is called a soft error or transient fault. In order to protect embedded systems from soft errors, conventional redundancy techniques such as TMR (Triple Modular Redundancy) and ECC (Error Correction Codes) incur high overheads in terms of area, power, and performance. For instance, the overheads of hardware and power for conventional TMR, which typically uses three functionally equivalent replicas of a logic circuit and a majority voter, exceed 200%. Since embedded systems are constrained with limited resources such as area, power and performance, there need several emerging challenges that embedded system designers are facing at microarchitectural level, at compilation, and at system level. For dependable embedded systems against soft error threats, solutions should accomplish high reliability with least overheads of power, performance, and area cost.